1. Field of the Invention
The present invention relates to a static semiconductor memory device, and more particularly, to the improvement of a static random access memory (SRAM) cell.
2. Description of the Related Art
A prior art SRAM cell is constructed by a flip-flop formed by cross-coupled first and second inverters and transfer transistors connected between first and second nodes of the flip-flop and data lines. That is, the first inverter is formed by a first load resistor between a power supply line and the first node and a drive MOS transistor between the first node and a ground line. Similarly, the second inverter is formed by a second load resistor element between the power supply line and the second node and a second drive MOS transistor between the second node and the ground line. In this SRAM cell, in order to increase the access speed, a salidation technology has been adopted. For example, the gate electrodes are constructed by a double configuration made of polycrystalline silicon and metal silicide. This will be explained later in detail.
In the above-described prior art SRAM cell however, since the load resistors are formed on the same plane as the gates of the drive transistors and the transfer transistors, the area of the SRAM cell is increased, which is disadvantageous in terms of integration.
If the load resistor is formed over the gates of the drive transistors, a parasitic resistance between the gate of the drive transistor and the source of the transfer transistor at the node is increased, thus remarkably decreasing the access speed of the SRAM cell. This also will be explained later in detail.